Dividing a single phase pulse-width modulation signal into a plurality of phases

ABSTRACT

Dividing a single phase PWM signal into a plurality of phases includes: receiving, from a phase controller by a PWM frequency divider, an input pulse train comprising a period; and dividing, by the PWM frequency divider, the input pulse train amongst a plurality of output phases of the PWM frequency divider, including, at the onset of each period of the input pulse train: providing, on a next output phase of the PWM frequency divider, an output pulse train; and holding all other output phases at a tri-state voltage level.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The field of the invention is data processing, or, more specifically, methods and apparatus for dividing a single phase pulse-width modulation (PWM) signal into a plurality of phases.

2. Description of Related Art

Computer system technology is continually advancing. Data centers, for example, now include hundreds or thousands of servers. Given the number of servers in a data center, decreasing the physical size or ‘footprint’ of the servers is a top priority for server system and server component designers. One area of focus, for example, is in reducing the size of Direct Current (‘DC’)-DC converters that distribute DC power amongst components of servers and the like.

In current art, reducing the size of such DC-DC converters is limited, at least in part, by the need for a plurality of output inductors and a filter capacitor. Some DC-DC converters of the prior art have implemented designs to somewhat reduce the physical footprint of the inductors and the capacitor by utilizing a single magnetic core for multiple inductors—an implementation of an indirectly coupled inductor. FIG. 1, for example, sets forth a prior art DC-DC converter that includes an indirectly coupled inductor.

The example DC-DC converter (100) of FIG. 1 includes two power-switching phases (132, 134). Each phase includes two switches: a high-side switch (102, 106), and a low-side switch (104, 108). Each high-side switch (102, 106) includes a control input (110, 114) to activate the switch. Upon activation, each high-side switch (102, 106) couples a voltage source (V_(IN)) to an indirectly coupled inductor (118). Each low-side switch (104, 108) also includes a control input (112, 116) to activate the switch. Upon activation, each low-side switch (104, 108) couples one coil of indirectly coupled inductor (118) to a ground voltage.

Coupled inductors come in two forms: indirectly coupled and directly coupled. The dots depicted in the example of FIG. 1 indicate the coupled inductor (118) is an indirectly coupled inductor. The dot convention specifies the flow of current in a coupled inductor as: when current flows ‘into’ one dot, current is induced in the alternate coil of the coupled inductor and flows ‘out of’ the other dot. Thus, in an indirectly coupled inductor, current generally flows in the same direction in both coils of the coupled inductor.

The example prior art DC-DC converter (100) of FIG. 1 also includes an output capacitor (120) that operates as a filter and a load, represented by a resistor (122).

FIG. 2 sets forth an example timing diagram (130) of activating the switches (102, 112, 106, 116) of the prior art DC-DC converter (100) of FIG. 1. In the example timing diagram of FIG. 2, switch (102) is activated between time T₀ and T₁, then deactivated from T₁ through T₃. Switch (112) is not activated from time T₀ and T₁, but is activated at time T₁ through T₃. Switch (114) is only activated between time T₂ to T₃. Switch (116) is activated from time T₀ to T₂ and activated again at time T₃.

The timing diagram (130) in the example of FIG. 2 specifies that activation of the high-side switch and low-side switch in a single phase of the prior art DC-DC converter (100) of FIG. 1 is asynchronous. Further, during any one given time period, two of the switches are activated at the same time. Although the indirectly coupled inductor in the example prior art DC-DC converter (100) of FIG. 1 represents a reduction in size relative to two, discrete inductors, operating the indirectly coupled prior art DC-DC converter (100) in accordance with the timing diagram of FIG. 2 limits any further inductor and capacitance reduction due to many factors, including for example: efficiency, current ripple, and so on.

SUMMARY OF THE INVENTION

Methods and apparatus for dividing a single phase PWM signal into a plurality of phases are described in this specification. Such division of a single phase PWM signal into a plurality of phases includes: receiving, from a phase controller by a PWM frequency divider, an input pulse train comprising a period; and dividing, by the PWM frequency divider, the input pulse train amongst a plurality of output phases of the PWM frequency divider, including, at the onset of each period of the input pulse train: providing, on a next output phase of the PWM frequency divider, an output pulse train; and holding all other output phases at a tri-state voltage level.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular descriptions of exemplary embodiments of the invention as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts of exemplary embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 sets forth a prior art DC-DC converter that includes an indirectly coupled inductor.

FIG. 2 sets forth an example timing diagram of activating the switches of the prior art DC-DC converter of FIG. 1.

FIG. 3 sets forth sets forth an identity switching DC-DC converter that includes a directly coupled inductor, operated in accordance with embodiments of the present invention.

FIG. 4 sets forth an example timing diagram of activating switches of the identity switching DC-DC converter of FIG. 3.

FIG. 5 sets forth an identity switching DC-DC converter that includes a plurality of power-switching phases and is controlled by a PWM frequency divider configured for operation in accordance with embodiments of the present invention.

FIG. 6 sets forth an example timing diagram of signals received and outputted by a PWM frequency divider operating in accordance with embodiments of the present invention.

FIG. 7 sets forth a flow chart illustrating an exemplary method for dividing a single phase PWM signal into a plurality of phases.

FIG. 8 sets forth a flow chart illustrating another exemplary method for dividing a single phase PWM signal into a plurality of phases.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Exemplary methods and dividing a single phase pulse-width modulation (PWM) signal into a plurality of phases in accordance with embodiments of the present invention are described with reference to the accompanying drawings, beginning with FIG. 3. As explained below in greater detail, such a multi-phase division of a PWM signal may control operation of a DC-DC converter in what is referred to in this specification as an identity switching matrix. For further explanation therefore, Figured 3 sets forth an identity switching DC-DC converter that includes a directly coupled inductor, operated in accordance with embodiments of the present invention.

The example identity switching DC-DC converter (200) of FIG. 3 includes a directly coupled inductor (218) that includes a first coil element and a second coil element. The first coil element and second coil element are coupled to an output filter—the capacitor (220)—and a load represented by a resistor (222). Unlike the prior art indirectly coupled inductor (118) of FIG. 1, in the directly coupled inductor (218) in the example of FIG. 3, current generally flows in the opposite direction in the coils of the coupled inductor. That is, when current enters one dot, current is induced to exit the other dot.

The example identity switching DC-DC converter (200) of FIG. 3 also includes two power-switching phases (232, 234). A first power-switching phase (232) includes a high-side switch (202) and a low-side switch (204). The high-side switch (202) is configured, when activated by a control input (210), to couple a voltage source (V_(IN)) to the first coil element of the directly coupled inductor (218). The low-side switch (204) is configured, when activated by a control input (212), to couple the first coil element to a ground voltage.

The second power-switching phase (234) of the example identity switching DC-DC converter (200) of FIG. 3 includes a high-side switch (206) and a low-side switch (208). The high-side switch (206) of the second power-switching phase (234) is configured, when activated by a control input (214), to couple the voltage source (V_(IN)) to the second coil element of the directly coupled inductor (218). The low-side switch (208) of the second power-switching phase (234) is configured, when activated by a control input (216), to couple the second coil element to the ground voltage.

As will occur to readers of skill in the art, each of the switches (202, 204, 206, 208) in the example of FIG. 3 may be implemented as a Field Effect Transistor (‘FET’) or the like.

The identity switching DC-DC converter (200) of FIG. 3 is operated by alternatively activating each switch, where no two switches are activated at the same time. For further explanation, FIG. 4 sets forth an example timing diagram of activating switches of the identity switching DC-DC converter of FIG. 3.

The DC-DC converter of FIG. 3 is described as an ‘identity switching’ converter due to the pattern of activating switches when viewed in a matrix or table. The example table below describes the timing of the switch activations as seen in the example timing diagram of FIG. 4:

TABLE 1 Switch Activation Pattern For Identity Switching DC-DC Converter (200) of FIG. 3 Control Input, Switch T₀-T₁ T₁-T₂ T₂-T₃ T₃-T₄ CI (210), HS Switch (202) 1 0 0 0 CI (212), LS Switch (204) 0 1 0 0 CI (214), HS Switch (206) 0 0 1 0 CI (216), LS Switch (208) 0 0 0 1

In the example Table 1 above, it can be seen that the control input and associated switches are alternatively activated (represented by a ‘1’ in the table) in a manner that forms an identity of the table. Further, no two switches are activated at the same time. As depicted in Table 1 and the example timing diagram (230) of FIG. 4: from time T₀-T₁, only the high-side switch (202) of the first power-switching phase (232) is activated; from time T₁-T₂, only the low-side switch (204) of the first power-switching phase (232) is activated; from time T₂-T₃, only the high-side switch (206) of the second power-switching phase (234) is activated; and from time T₃-T₄, only the low-side switch (208) of the second power-switching phase (234) is activated. In this way, each phase is utilized at a 180 degree offset and each high-side switch for a period of time according to:

$\frac{D}{N},$ where D represents a duty cycle and N represents the number of power-switching phases. Each low-side switch is therefore activated for a period of time according to:

$\frac{\left( {1 - D} \right)}{N}.$

In this way, the number of phases is inversely proportional to the duty cycle of activating the switches—that is, the ‘effective’ duty cycle—and thereby is inversely proportional to the inductance of the directly coupled inductor. Increasing the number of phases, therefore, decreases the inductance.

And the transfer function of the identity switching DC-DC converter (200) of FIG. 3, when operated in accordance with the identity switching scheme in Table 1 and the timing diagram (230) of FIG. 4 is:

$\frac{V_{OUT}}{V_{IN}} = \frac{D}{N}$

Operating the example identity switching DC-DC converter (200) of FIG. 3 in accordance with the identity switching scheme in Table 1 and the timing diagram of FIG. 4 enables energy to be stored between deactivating the low-side switch (212) of the first power-switching phase (232) and activation of the high-side switch of the second power-switching phase (234), thus increasing overall system efficiency and reducing current ripple. That is, current ripple experienced by the magnetic core of the directly coupled inductor (218) and the output capacitor (220) is reduced, relative to circuits of the prior art, due in part to the effective reduced duty cycle of the switch activations. The current ripple experienced by the output filter capacitor (220) and the load (222) may be calculated as:

${\frac{1}{f*L_{OL}}*\left( {1 - \frac{V_{OUT}}{V_{IN}}} \right)*\frac{V_{OUT}}{N}},$ where f represents the frequency of alternatively activating each switch, L_(OL) represents the open loop inductance of the directly coupled inductor, N represents the number of power-switching phases, V_(IN) represents the voltage of the voltage source and V_(OUT) represents the voltage experienced at the filter and load.

FIGS. 3 and 4 generally depict an identity switching DC-DC converter configured with two phases and operation thereof, but readers of skill in the art will recognize that an identity switching DC-DC converter operated in accordance with embodiments of the present invention may have any number of phases. Further, the control inputs (210, 212, 214, and 216) receive a control signal from a source. In some embodiments, that source is a PWM frequency divider. For further explanation therefore, FIG. 5 sets forth an identity switching DC-DC converter that includes a plurality of power-switching phases and is controlled by a PWM frequency divider configured for operation in accordance with embodiments of the present invention.

The example DC-DC converter of FIG. 5 is similar the DC-DC converter of FIG. 3 in that the example DC-DC converter (500) includes a plurality of power-switching phases (232, 234, 520, 522) and a directly coupled inductor (218, 524). The directly coupled inductor (218, 524) includes a coil element. Each power-switching phase includes a high-side switch (202, 206) and a low-side switch (204, 208). The switches of the phases (520, 522) are not shown here for purposes of simplicity, but are configured similar to the other phases (232, 234). The high-side switch (202, 206) of each phase (232, 234, 520, 522) is configured, when activated, to couple a voltage source (V_(IN)) to the coil element and the low-side switch (204, 208) is configured, when activated, to couple the coil element to a ground voltage. The coil element is coupled to an output filter (220) and a load (222).

The example identity switching DC-DC converter (500) of FIG. 5 differs from that of FIG. 3, however, in that the each of power-switching phases (232, 234, 520, 522) also includes a driver (510) configured to activate the high and low side switches of the phase. The driver (510) in the example of FIG. 5 may be implemented in a variety of ways including, for example, as a field programmable gate array (FPGA), application specific integrated circuit (ASIC), analog circuitry, digital circuitry, or some combination of such circuitry. The driver (508, 510) activates each switch via outputs (526, 528, 530, 532) of the driver responsive to a signal received at the input of the driver. The driver receives such a signal from a PWM frequency divider (506).

A PWM frequency divider may be implemented in a variety of ways including, for example, with an FPGA, ASIC, digital logic, analog circuitry, or some combination of such devices. The example PWM frequency divider (506) of FIG. 5 is configured to: receive, from a phase controller (502), an input pulse train (502). A pulse train, as the term is used in this specification, refers to a signal that repetitively varies between a logic high voltage level and a logic low voltage level, such as a square wave. Each repetition of the signal occurs within a period. Each period includes a transition to a logic high voltage level and a transition to a logic low voltage level. The phase controller (502) that provides such a signal in the example of FIG. 5 may be any type of circuitry including digital, analog or some combination. In some embodiments, the phase controller may be a clock generator for a system in which the DC-DC converter (500) is a component.

The PWM frequency divider (506) in the example of FIG. 5 is also configured to divide the input pulse train (504) amongst a plurality of output phases (512, 514, 516, 518). The PWM frequency divider (506) divides the input pulse train amongst the output phases by carrying out the following steps at the onset of each period of the input pulse train: providing, on a next output phase of the PWM frequency divider, an output pulse train and holding all other output phases at a tri-state voltage level. The signal provided on the output phase to each driver transitions between one of three states: logic high, tri-state, and logic low. Consider, for example, that logic high is 1 volt (V), logic low is −1 V and tri-state is 0 V. At the onset of each period of the input pulse train the PWM frequency divider (506) provides a ‘next’ output phase with an output pulse train (a signal that varies from logic high to logic low) and ensures that all other output phases are at the tri-state voltage level. The term ‘next’ here refers to the fact that the frequency divider provides the output pulse train signal to each output phase cyclically. In FIG. 5, for example, the PWM frequency divider (506) may provide the output pulse train on output phase (512), while holding all other output phases (514, 516, 518) at a tri-state voltage level. Then, at the outset of the next period of the input pulse train, the PWM frequency divider may provide the output pulse train on output phase (514) while holding all other output phases (512, 516, 518) at the tri-state voltage level. This cycle may continue so that the PWM frequency divider (506) provides the output pulse train to output phase (516), then to output phase (518). At this point, the PWM frequency divider (506) may cycle back and provide the output pulse train on output phase (512) where the cycles will continue indefinitely.

The cyclical nature of the PWM frequency divider (506) is illustrated in FIG. 6. Turning briefly there, FIG. 6 sets forth an example timing diagram (612) of signals received and outputted by a PWM frequency divider operating in accordance with embodiments of the present invention. In FIG. 6, signal (602) is the input pulse train received by the PWM frequency divider. Signals (604-610) are the signals provided by the PWM frequency divider on separate output phases. Signal (604), for example, may be the signal carried by output phase (512 of FIG. 5), signal (606) may be the signal carried by output phase (514 of FIG. 5), signal (608) may be the signal carried by output phase (516 of FIG. 5), and signal (608) may be the signal carried by output phase (516 of FIG. 5).

Beginning at time T₀, the input pulse train begins a period in which the input pulse train transition from logic high and returns to logic low. At the onset of that period, the PWM frequency divider provides on the signal (602) of the first output phase, an output pulse train that transitions from a tri-state voltage, to logic high, then to logic low at the end of the period of the input pulse train. During this period, the PWM frequency divider holds the signal carried on all other output phases at the tri-state voltage level.

At time T₁, a second period of the input pulse train begins. At this time, the PWM frequency divider provides the output pulse train on the next output phase—the signal (606) carried by the second output phase. The output pulse train again transitions from the tri-state voltage level to logic high then to logic low. During this period of the output pulse train, the signals of the other output phases are held to the tri-state voltage level.

The above steps repeat for each subsequent period of the input pulse train until the PWM frequency divider provides an output pulse train on each of the signals carried by each of the output phases. When all output phases have carried the output pulse train, the PWM begins the process again with the first output phase.

Returning now to FIG. 5, the PWM frequency divider (506) provides the output pulse train on output phases coupled to the drivers (508, 510) of each of the power-switching phases (232, 234, 520, 522) of the DC-DC converter (500). As mentioned above, the driver (508, 510) of each phase is configured to activate the high side switch and the low side switch of each power-switching phase responsive to the signal received at the input of the driver; the signal received on the output phase of the PWM frequency divider. To that end, each driver (508, 510) is configured to:

-   -   activate the high side switch and deactivate the low side switch         when the output pulse train of the output phase is a logic high         voltage level, activate the low side switch and deactivate the         high side switch when the output pulse train of the output phase         is a logic low voltage level, and     -   deactivate the high and low side switches when the output pulse         train of the output phase is a tri-state voltage level.

In this way, when a driver receives the output pulse train from the PWM frequency divider, the driver first activates the high side switch while keeping the low side switch deactivated, then activates the low side switch and deactivates the high side switch. When the driver receives the tri-state voltage (all other times than when receiving the output pulse train) from the PWM frequency divider, the driver deactivates both switches. As the PWM frequency divider provides the output pulse train to each driver separately and cyclically and at all other times provides each driver with the tri-state voltage, an identity switching control scheme like those described above is employed in the example of FIG. 5.

For further explanation, FIG. 7 sets forth a flow chart illustrating an exemplary method for dividing a single phase PWM signal into a plurality of phases. The method of FIG. 7 includes receiving (702), from a phase controller by a PWM frequency divider, an input pulse train comprising a period. Receiving (702) an input pulse train may be carried out in various ways including, for example, by receiving a system clock signal from a clock generator.

The method of FIG. 7 also includes dividing (704), by the PWM frequency divider, the input pulse train amongst a plurality of output phases of the PWM frequency divider. In the example of FIG. 7, dividing (704), by the PWM frequency divider, the input pulse train amongst a plurality of output phases of the PWM frequency divider includes, at the onset of each period of the input pulse train: providing (706), on a next output phase of the PWM frequency divider, an output pulse train; and holding (708) all other output phases at a tri-state voltage level.

Providing (706) an output pulse train to a next output phase of the PWM frequency divider at the onset of each phase of the input pulse train may be carried out in various ways. In some embodiments, the PWM frequency divider may effectively operate with a cyclical counter that provides a selection signal to a multiplexer. The counter may increment upon the onset of each period of the input pulse train. The multiplexer may provide the signal received at an input to one of a plurality of outputs in dependence upon the selection signal received from the cyclical counter. The signal received at the input of the multiplexer may be the input pulse train itself. In this way, the input pulse train is provided to a single output of the multiplexer for a first period, then when the counter increments, the input pulse train is provided to a next output of the multiplexer for a second period, and so on.

Holding (708) output phases at a tri-state voltage level may also be carried out in various ways. In some embodiments, for example, each output phase may be coupled to a pull-down or pull-up resistor that couples the phase to the tri-state voltage.

FIG. 8 sets forth a flow chart illustrating another exemplary method for dividing a single phase PWM signal into a plurality of phases. The method of FIG. 8 is similar to the method of FIG. 7 in that the method of FIG. 8 also includes receiving (702) an input pulse train comprising a period and dividing (704) the input pulse train amongst a plurality of output phases of the PWM frequency divider. Also in the method of FIG. 8, dividing (704) the input pulse train is carried out by, at the onset of each period of the input pulse train, providing (706), on a next output phase of the PWM frequency divider, an output pulse train and holding (708) all other output phases at a tri-state voltage level.

The method of FIG. 8 differs from the method of FIG. 7, however, in that in the method of FIG. 8 the PWM frequency divider is coupled to a DC-DC converter via the plurality of output phases. Such a DC-DC converter may be similar to the DC-DC converter illustrated in FIG. 5, which includes a directly coupled inductor having a coil element coupled to an output filter and a load. The DC-DC converter may also include a plurality of power-switching phases, with each phase having a high-side switch, a low-side switch and a driver. Each switch may be implemented as a FET.

The high-side switch of each power-switching phase is configured, when activated via the driver, to couple a voltage source to the coil element and the low-side switch is configured, when activated via the driver, to couple the coil element to a ground voltage. The driver is coupled to one of the plurality of output phases of the PWM frequency divider and is configured to: activate the high side switch and deactivate the low side switch when the output pulse train of the output phase is a logic high voltage level; activate the low side switch and deactivate the high side switch when the output pulse train of the output phase is a logic low voltage level and the driver is configured to deactivate the high and low side switches when the output pulse train of the output phase is a tri-state voltage level.

The method of FIG. 8 also differs from the method of FIG. 7 in that the method of FIG. 8 includes alternately activating (802), by the drivers of the plurality of power-switching phases, each switch, where no two switches are activated at the same time responsive to receiving the output pulse train of the plurality of output phases of the frequency divider. Alternatively activating (802) each switch may be carried out by activating each high-side switch for a period of time according to:

$\frac{D}{N}$ where D represents a duty cycle and N represents the number of power-switching phases and activating each low-side switch for a period of time according to:

$\frac{\left( {1 - D} \right)}{N}.$

In some embodiments, the number of power-switching phases of the DC-DC converter may be inversely proportional to the duty cycle of activating the switches and thereby inversely proportional to the inductance of the directly coupled inductor. Also, the current ripple experienced by the filter and the load in such a DC-DC converter may be:

${\frac{1}{f*L_{OL}}*\left( {1 - \frac{V_{OUT}}{V_{IN}}} \right)*\frac{V_{OUT}}{N}},$ where f represents the frequency of alternatively activating each switch, L_(OL) represents the open loop inductance of the directly coupled inductor, N represents the number of power-switching phases, V_(IN) represents the voltage of the voltage source and V_(OUT) represents the voltage experienced at the filter and load.

It will be understood from the foregoing description that modifications and changes may be made in various embodiments of the present invention without departing from its true spirit. The descriptions in this specification are for purposes of illustration only and are not to be construed in a limiting sense. The scope of the present invention is limited only by the language of the following claims. 

What is claimed is:
 1. A method of dividing a single phase pulse-width modulation (PWM) signal into a plurality of phases, the method comprising: receiving, from a phase controller by a PWM frequency divider, an input pulse train comprising a period; and dividing, by the PWM frequency divider, the input pulse train amongst a plurality of output phases of the PWM frequency divider, including, at the onset of each period of the input pulse train: providing, on a next output phase of the PWM frequency divider, an output pulse train that transitions from a tri-state voltage level to a logic high voltage level at the onset of a period of the input pulse train and transitions from the logic high voltage level to a logic low voltage level toward the end of the period of the input pulse train; and holding all other output phases at the tri-state voltage level that is between the logic high voltage level and the logic low voltage level.
 2. The method of claim 1 wherein the PWM frequency divider is coupled to a Direct Current (DC)-DC converter via the plurality of output phases, the DC-DC converter comprising: a directly coupled inductor comprising a coil element coupled to an output filter and a load; and a plurality of power-switching phases, with each phase comprising a high-side switch, a low-side switch and a driver, wherein the high-side switch of each power-switching phase is configured, when activated via the driver, to couple a voltage source to the coil element and the low-side switch of each power-switching phase is configured, when activated via the driver, to couple the coil element to a ground voltage, wherein the driver is coupled to one of the plurality of output phases of the PWM frequency divider and the driver is configured to activate the high side switch and deactivate the low side switch when the output pulse train of the output phase is a logic high voltage level, the driver is configured to activate the low side switch and deactivate the high side switch when the output pulse train of the output phase is a logic low voltage level, and the driver is configured to deactivate the high and low side switches when the output pulse train of the output phase is a tri-state voltage level; and the method further comprises: responsive to receiving the output pulse train of the plurality of output phases of the frequency divider: alternately activating, by the drivers of the plurality of power-switching phases, each switch, wherein no two switches are activated at the same time.
 3. The method of claim 2 wherein alternatively activating each switch further comprises: activating each high-side switch for a period of time according to: $\frac{D}{N}$ where D represents a duty cycle and N represents the number of power-switching phases; and activating each low-side switch for a period of time according to: $\frac{\left( {1 - D} \right)}{N}.$
 4. The method of claim 2 wherein the number of power-switching phases is inversely proportional to the duty cycle of activating the switches and thereby inversely proportional to the inductance of the directly coupled inductor.
 5. The method of claim 2 wherein current ripple experienced by the filter and the load comprises: ${\frac{1}{f*L_{OL}}*\left( {1 - \frac{V_{OUT}}{V_{IN}}} \right)*\frac{V_{OUT}}{N}},$ where f represents the frequency of alternatively activating each switch, L_(OL) represents the open loop inductance of the directly coupled inductor, N represents the number of power-switching phases, V_(IN) represents the voltage of the voltage source and V_(OUT) represents the voltage experienced at the filter and load.
 6. The method of claim 2 wherein each high-side switch and each low-side switch comprises a Field Effect Transistor.
 7. The method of claim 1 wherein the PWM frequency divider comprises a Field Programmable Gate Array (FPGA).
 8. An apparatus for dividing a single phase pulse-width modulation (PWM) signal into a plurality of phases, the apparatus comprising a computer processor, a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the steps of: receiving, from a phase controller by a PWM frequency divider, an input pulse train comprising a period; and dividing, by the PWM frequency divider, the input pulse train amongst a plurality of output phases of the PWM frequency divider, including, at the onset of each period of the input pulse train: providing, on a next output phase of the PWM frequency divider, an output pulse train that transitions from a tri-state voltage level to a logic high voltage level at the onset of a period of the input pulse train and transitions from the logic high voltage level to a logic low voltage level toward the end of the period of the input pulse train; and holding all other output phases at the tri-state voltage level that is between the logic high voltage level and the logic low voltage level.
 9. The apparatus of claim 8 wherein the PWM frequency divider is coupled to a Direct Current (DC)-DC converter via the plurality of output phases, the DC-DC converter comprising: a directly coupled inductor comprising a coil element coupled to an output filter and a load; and a plurality of power-switching phases, with each phase comprising a high-side switch, a low-side switch and a driver, wherein the high-side switch of each power-switching phase is configured, when activated via the driver, to couple a voltage source to the coil element and the low-side switch of each power-switching phase is configured, when activated via the driver, to couple the coil element to a ground voltage, wherein the driver is coupled to one of the plurality of output phases of the PWM frequency divider and the driver is configured to activate the high side switch and deactivate the low side switch when the output pulse train of the output phase is a logic high voltage level, the driver is configured to activate the low side switch and deactivate the high side switch when the output pulse train of the output phase is a logic low voltage level, and the driver is configured to deactivate the high and low side switches when the output pulse train of the output phase is a tri-state voltage level; and the apparatus further comprises computer program instructions that when executed causes the apparatus to carry out the steps of: responsive to receiving the output pulse train of the plurality of output phases of the frequency divider: alternately activating, by the drivers of the plurality of power-switching phases, each switch, wherein no two switches are activated at the same time.
 10. The apparatus of claim 9 wherein alternatively activating each switch further comprises: activating each high-side switch for a period of time according to: $\frac{D}{N}$ where D represents a duty cycle and N represents the number of power-switching phases; and activating each low-side switch for a period of time according to: $\frac{\left( {1 - D} \right)}{N}.$
 11. The apparatus of claim 9 wherein the number of power-switching phases is inversely proportional to the duty cycle of activating the switches and thereby inversely proportional to the inductance of the directly coupled inductor.
 12. The apparatus of claim 9 wherein current ripple experienced by the filter and the load comprises: ${\frac{1}{f*L_{OL}}*\left( {1 - \frac{V_{OUT}}{V_{IN}}} \right)*\frac{V_{OUT}}{N}},$ where f represents the frequency of alternatively activating each switch, L_(OL) represents the open loop inductance of the directly coupled inductor, N represents the number of power-switching phases, V_(IN) represents the voltage of the voltage source and V_(OUT) represents the voltage experienced at the filter and load.
 13. The apparatus of claim 9 wherein each high-side switch and each low-side switch comprises a Field Effect Transistor.
 14. The apparatus of claim 8 wherein the PWM frequency divider comprises a Field Programmable Gate Array (FPGA). 